The present invention relates to a method for manufacturing a semiconductor device.
A conventional high breakdown voltage MOS transistor has a structure wherein in order to relax an electric field lying under a gate electrode thereby to suppress the occurrence of hot carriers, low-concentration diffusion layers with an impurity diffused therein in a low concentration overlap beneath the gate electrode.
In order to more reduce the size of the transistor having this type of structure, there has been proposed a technique for forming each of slits in at least a region on the drain electrode side, of a gate electrode (refer to a patent document 1 (Japanese Patent Application Laid-open No. 2005-142475)).
In the present technique, a semiconductor device is manufactured through the following steps of: (1) forming a gate insulating film on a first conductivity-type layer of a semiconductor substrate, (2) forming on the gate insulating film, a gate electrode having slits each provided at at least one end on the drain electrode forming predetermined side, (3) selectively implanting a second conductivity-type impurity into the first conductivity-type layer with the gate electrode as a mask, (4) performing heat treatment thereby to activate the impurity and bringing regions of the impurity implanted into the slits and regions of the impurity implanted in the outside of the gate electrode, which are lying in the neighborhood of the slits into integral form, thereby forming a pair of second conductivity-type layers each of which overlaps with at least one side on the drain electrode forming predetermined side, of the gate electrode, and (5) forming within the pair of second conductivity-type layers, a pair of second conductivity-type high-concentration layers separated from the gate electrode and for contacting a source electrode and the drain electrode respectively.
In this semiconductor device fabrication process, the impurity implantation step is executed twice (step (3) and step (5)). The thermal diffusion step for thermally diffusing the impurity in a substrate plane direction is executed once (step (4)) to couple the two impurity diffusion regions placed in a separated state.
There has also been proposed a technique for fabricating a semiconductor device having a structure approximately similar to the semiconductor device shown in the patent document 1 in accordance with a completely separate process (refer to a patent document 2 (Japanese Patent Application Laid-open No. 2002-289845)).
In the present technique, a semiconductor device is manufactured through the following steps of: (1) implanting reverse conductivity-type ions into a surface layer of a semiconductor layer of one conductivity type in a low concentration thereby to selectively form a first offset region of a reverse conductivity type in a low concentration, (2) selectively simultaneously forming a gate electrode at the surface layer of the semiconductor layer outside lying on the first offset region through a gate oxide film interposed therebetween and a spacer layer with the same material as the gate electrode and apart from the gate electrode over the first offset region, (3) implanting reverse conductivity-type ions into the surface layer of the semiconductor layer through the gate electrode in a low concentration thereby to form a low-concentration and reverse conductivity-type second offset region aligned with an end of the gate electrode and brought into contact with the first offset region, (4) forming a coated insulating film so as to cover the surface of the semiconductor layer and performing anisotropic etching on the coated insulating film to leave part of the coated insulating film between the same and the spacer layer, thereby forming sidewall spacer films on sidewall portions of the spacer layer, and (5) implanting reverse conductivity-type ions through the sidewall spacer films in a high concentration thereby to form high-concentration and reverse conductivity-type source/drain regions aligned with the ends of the sidewall spacer films.
In this manufacture process, the step (2) corresponds to the slit forming step employed in the invention described in the patent document 1, and the step of implanting the impurity (ions) is executed three times (steps (1), (3) and (5)).
In the conventional manufacturing method, however, the step of implanting the impurity and the step of thermally diffusing the once-implanted impurity must be executed three times, and its manufacturing process has been complicated.